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Metrology and Diagnostic Techniques for Nanoelectronics
edited by Zhiyong Ma and David G. Seiler
- Format: eBook
- ISBN: 9789814745093
- Subject: Nanotechnology and Nanomaterials
- Published: October 2016
- Pages: 1411
For Course Instructors: Inspection Copies
Nanoelectronics is changing the way how the world is communicated and is transforming our daily life. Continued Moore’s law scaling and miniaturization of low power semiconductor chips with ever increasing functionality in the past decade have been relentlessly driving research and development of new devices, materials, and process capabilities to meet performance, power and cost requirement. This book is designed to review the most recent work and results for selected important metrology and diagnostics topics being encountered in continuing Moore’s law scaling and product development. It is intended for a broad audience that is involved in all aspects of IC manufacturing and nanoelectronics from research to development to manufacturing. It can also serve as a reference book for those who study process and assembly technologies used in nanoelectronics or are involved in device testing, characterization, and diagnostic techniques.
The book is composed of twenty-five chapters divided into five parts covering characterization techniques and metrology for transistors, interconnects, defects, and emerging materials and devices, diagnostic methods and techniques for product debug and yield enhancement, and package fault isolation and defect imaging for 3D interconnects. The chapter authors are from academia, government labs, and industry, and have vast experiences and expertise in the topics presented.
About the Editors:
Zhiyong Ma has a bachelor’s degree in metallurgical engineering from Shanghai University of Technology, China; a master’s degree in materials engineering from Purdue University, Indiana; and a PhD in materials science and engineering from the University of Illinois, Urbana-Champaign. Dr. Ma worked at Digital Equipment Corporation as a senior process engineer in thin-film metallization and processing. He joined Intel’s Corporate Quality Network in 1995 as a senior process engineer. Currently, he is vice president of the Technology and Manufacturing Group and director of Technology Development and Manufacturing Labs at Intel, responsible for labs operations in support of silicon and assembly technology development and manufacturing, product fault diagnostics, and silicon and platform benchmarking, including strategic business planning, analytical technique development, metrology roadmaps, and fostering of innovation in lab metrology and diagnostic tool development. Dr. Ma holds 6 patents in underbump metallization, strained silicon transistors, secured fuse technology, and silicon diagnostic techniques and has published more than 25 refereed papers, as well as a book chapter on silicide technology. His research interests include thin-film kinetics, analytical techniques and metrology, and product fault diagnostics.
David G. Seiler received his PhD and MS in physics from Purdue University and a BS in physics from Case Western Reserve University, Ohio. In 2000, he received a Distinguished Alumni Award from Purdue University's School of Science for his contributions to and achievements in semiconductors. Dr. Seiler served as solid state physics program director in the Materials Research Division, National Science Foundation; spent a year's sabbatical at the MIT Francis Bitter National Magnet Laboratory; and was a regents’ professor of physics at the University of North Texas. He joined the National Institute of Standards and Technology (NIST) in 1988 and served as program analyst in the program office for the director of NIST and as materials technology group leader in the Engineering Physics Division. Currently, he is chief of the division, which provides technical leadership in measurement science research, development, and standards essential to improving US economic competitiveness for advanced manufacturing. Dr. Seiler has been the chairperson and proceedings editor of 13 international conferences or workshops. He is the co-editor and the co-author of a chapter in Semiconductors and Semimetals (1992, Vol. 36) and a co-author of a chapter in Handbook of Optics (1995). He is also a co-editor of journals and books containing the proceedings from 9 international conferences and workshops. His current research focus is on understanding and advancing the metrology and characterization measurements needed by the semiconductor industry. The results of his research have been disseminated in over 200 publications and 100 talks throughout the world.
Chapter 1
Model-Based Scanning Electron Microscopy Critical-Dimension Metrology for 3D Nanostructures
András E. Vladár
Pages: 3
USD $34.95
Add to cartChapter 2
X-Ray Metrology for Semiconductor Fabrication
Daniel F. Sunday and R. Joseph Kline
Pages: 31
USD $34.95
Add to cartChapter 3
Advancements in Ellipsometric and Scatterometric Analysis
Samuel O’Mullane, Dhairya Dixit, and Alain C. Diebold
Pages: 65
USD $34.95
Add to cartChapter 4
3D-AFM Measurements for Semiconductor Structures and Devices
Ndubuisi G. Orji and Ronald G. Dixson
Pages: 109
USD $34.95
Add to cartChapter 5
SIMS Analysis on the Transistor Scale: Probing Composition and Dopants in Nonplanar, Confined 3D Volumes
Andre A. Budrevich and Wilfried Vandervorst
Pages: 153
USD $34.95
Add to cartChapter 6
Transistor Strain Measurement Techniques and Their Applications
Markus Kuhn, Stephen Cea, Jiong Zhang, Matthew Wormington, Thomas Nuytten, Ingrid De Wolf , Jian-Min Zuo, and Jean-Luc Rouviere
Pages: 207
USD $34.95
Add to cartChapter 7
Scanning Spreading Resistance Microscopy (SSRM): High-Resolution 2D and 3D Carrier Mapping of Semiconductor Nanostructures
Andreas Schulze, Pierre Eyben, Thomas Hantschel, and Wilfried Vandervorst
Pages: 377
USD $34.95
Add to cartChapter 8
Microstructure Characterization of Nanoscale Materials and Interconnects
J. K. Weiss, Jai Ganesh Kameswaran, Amith Darbal, Jiong Zhang, Di Xu, and Edgar F. Rauch
Pages: 447
USD $34.95
Add to cartChapter 9
Characterization of the Chemistry and Mechanical Properties of Interconnect Materials and Interfaces: Impact on Interconnect Reliability
Ying Zhou and Han Li
Pages: 493
USD $34.95
Add to cartChapter 10
Characterization of Plasma Damage for Low-k Dielectric Films
Hualiang Shi, Huai Huang, Ryan S. Smith, and Paul S. Ho
Pages: 541
USD $34.95
Add to cartChapter 11
Defect Characterization and Metrology
Tuyen K. Tran
Pages: 589
USD $34.95
Add to cartChapter 12
3D Electron Tomography for Nanostructures
Huolin L. Xin, Sai Bharadwaj Vishnubhotla, and Ruoqian Lin
Pages: 637
USD $34.95
Add to cartChapter 13
Electron Energy Loss Spectroscopy of Semiconductor Nanostructures and Oxides
Wu Zhou, Maria Varela, Juan-Carlos Idrobo, Sokrates T. Pantelides, and Stephen J. Pennycook
Pages: 663
USD $34.95
Add to cartChapter 14
Atom Probe Tomography of Semiconductor Nanostructures
Thomas F. Kelly and Karen Henry
Pages: 711
USD $34.95
Add to cartChapter 15
Characterization and Metrology for Graphene Materials, Structures, and Devices
Luigi Colombo, Alain Diebold, Cinzia Casiraghi, Moon Kim, Robert M. Wallace, and Archana Venugopal
Pages: 759
USD $34.95
Add to cartChapter 16
Characterization of Magnetic Nanostructures for Spin-Torque Memory Applications with Macro- and Microscale Ferromagnetic Resonance
T. J. Silva, H. T. Nembach, J. M. Shaw, Brian Doyle, Kaan Oguz, Kevin O’brien, and Mark Doczy
Pages: 849
USD $34.95
Add to cartChapter 17
Band Alignment Measurement by Internal Photoemission Spectroscopy
Nhan V. Nguyen
Pages: 891
USD $34.95
Add to cartChapter 18
Electrical Characterization of Nanoscale Transistors: Emphasis on Traps Associated with MOS Gate Stacks
Xiao Sun and T. P. Ma
Pages: 933
USD $34.95
Add to cartChapter 19
Charge Pumping for Reliability Characterization and Testing of Nanoelectronic Devices
Jason T. Ryan, Jason P. Campbell, Kin P. Cheung, and John S. Suehle
Pages: 977
USD $34.95
Add to cartChapter 20
Application of in situ Resistance and Nanocalorimetry Measurements for Nanoelectronic Thin-Film Materials
Zichao Ye, Zhiyong Ma, and Leslie H. Allen
Pages: 1013
USD $34.95
Add to cartChapter 21
Methodology and Challenges in Characterization of 3D Package Interconnection Materials and Processes
Rajen Dias and Deepak Goyal
Pages: 1089
USD $34.95
Add to cartChapter 22
3D Interconnect Characterization Using Raman Spectroscopy
Ingrid De Wolf
Pages: 1121
USD $34.95
Add to cartChapter 23
Advances in 3D Interconnect Characterization Techniques for Fault Isolation and Defect Imaging
Wenbing Yun, Mario Pacheco, Sebastian Brand, Peter Czurratis, Matthias Petzold, Tatjana Djuric, Peter Hoffrogge, Mayue Xie, Deepak Goyal, Zhiyong Wang, Antonio Orozco, Fred C. Wellstood, and Rajen Dias
Pages: 1147
USD $34.95
Add to cartChapter 24
Optical and Electrical Nanoprobing for Circuit Diagnostics
Travis Eiles, Tom Tong and Edward I. Cole, Jr.
Pages: 1275
USD $34.95
Add to cartChapter 25
Automated Tools and Methods for Debug and Diagnosis
Srikanth Venkataraman
Pages: 1347
USD $34.95
Add to cartZhiyong Ma received his MS degree in materials engineering from Purdue University, Indiana, and a PhD in materials science and engineering from the University of Illinois, Urbana-Champaign. He worked in thin-film metallization and processing at Digital Equipment Corporation and joined Intel’s Corporate Quality Network in 1995. Currently, he is vice president of the Technology and Manufacturing Group and
director of Technology Development and Manufacturing Labs at Intel, responsible for the CQN lab network in support of silicon and assembly technology development and manufacturing, product fault diagnostics, and silicon and platform benchmarking, including strategic business
planning, analytical technique development, and metrology roadmaps. Dr. Ma holds 8 patents in underbump metallization, strained silicon transistors, secured fuse technology, and silicon diagnostic techniques, has published more than 25 refereed papers, and has coauthored a book chapter
on silicide technology. His research interests include thin-film kinetics, analytical techniques and metrology, and product fault diagnostics.
David G. Seiler received his PhD and MS in physics from Purdue University and a BS in physics from Case Western Reserve University, Ohio. He is a fellow of the American
Physical Society and a fellow of the Institute of Electrical and Electronic Engineers. In 2000, he received a Distinguished Alumni Award from Purdue University’s School of Science for his contributions to and achievements in semiconductors. He
served as solid state physics program director in the Materials Research Division, National Science Foundation; spent a year’s sabbatical at the MIT Francis Bitter National Magnet
Laboratory; and was a regents’ professor of physics at the University of North Texas. He joined the National Institute of Standards and Technology (NIST) in 1988 and served as program analyst in the program office for the director of NIST and as materials technology group leader in the Engineering
Physics Division. Currently, he is chief of the division, which provides technical leadership in measurement science research, development, and standards essential to improving US economic competitiveness for advanced manufacturing. Dr. Seiler has been the chairperson and proceedings
editor of 15 international conferences or workshops. He is the coeditor and coauthor of a chapter in Semiconductors and Semimetals (1992, Vol. 36) and a coauthor of a chapter in Handbook of Optics (1995, revised 2009). His current research focus is on understanding and advancing the metrology and characterization measurements needed for the future of nanoelectronics. The results of his research have been disseminated in over 200 publications and 100 talks throughout the world.